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HEF4516B
Binary up/down counter
Rev. 06 -- 11 December 2009 Product data sheet
1. General description
The HEF4516B is an edge-triggered synchronous 4-bit binary up/down counter with a clock input (CP), an up/down count control input (UP/DN), an active LOW count enable input (CE), an asynchronous active HIGH parallel load input (PL), four parallel inputs (D0 to D3), four parallel outputs (Q0 to Q3), an active LOW terminal count output (TC), and an overriding asynchronous master reset input (MR). Information on D0 to D3 is loaded into the counter while PL is HIGH, independent of all other input conditions except for MR which must be LOW. When PL and CE are LOW, the counter changes on the LOW-to-HIGH transition of CP. Input UP/DN determines the direction of the count, counting up when HIGH and counting down when LOW. When counting up, TC is LOW when Q0 and Q3 are HIGH and CE is LOW. When counting down, TC is LOW when Q0 to Q3 and CE are LOW. A HIGH on MR resets the counter (Q0 to Q3 = LOW) independent of all other input conditions. It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS (usually ground). Unused inputs must be connected to VDD, VSS, or another input. It is also suitable for use over the full industrial (-40 C to +85 C) temperature range.
2. Features
Fully static operation 5 V, 10 V, and 15 V parametric ratings Standardized symmetrical output characteristics Operates across the full industrial temperature range -40 C to +85 C Complies with JEDEC standard JESD 13-B
3. Applications
Industrial
4. Ordering information
Table 1. Ordering information All types operate from -40 C to +85 C. Type number HEF4516BP HEF4516BT Package Name DIP16 SO16 Description plastic dual in-line package; 16-leads (300 mil) plastic small outline package; 16 leads; body width 3.9 mm Version SOT38-4 SOT109-1
NXP Semiconductors
HEF4516B
Binary up/down counter
5. Functional diagram
4 D0 PL 12 D1 13 D2 3 D3
1
PARALLEL LOAD CIRCUITRY
15 5 10 9
CP CE UP/DN MR
SD/CD UP/DOWN COUNTER CD Q0 6 Q1 11 Q2 14 2 Q3
001aae667
TC
7
Fig 1.
Functional diagram
HEF4516B_6
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 06 -- 11 December 2009
2 of 16
NXP Semiconductors
HEF4516B
Binary up/down counter
D1 MR
D2
D3
D4
PL
CP
UP/DN J SD FF1 CE CP Q J SD FF2 CP Q J SD FF3 CP Q J SD FF4 CP Q
K
CD
Q
K
CD
Q
K
CD
Q
K
CD
Q
Q0
Q1
Q2
Q3
TC
001aaj798
Fig 2.
Logic diagram
HEF4516B_6
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 06 -- 11 December 2009
3 of 16
NXP Semiconductors
HEF4516B
Binary up/down counter
6. Pinning information
6.1 Pinning
HEF4516B
PL Q3 D3 D0 CE Q0 TC VSS 1 2 3 4 5 6 7 8
001aae689
16 VDD 15 CP 14 Q2 13 D2 12 D1 11 Q1 10 UP/DN 9 MR
Fig 3.
Pin configuration
6.2 Pin description
Table 2. Symbol PL D0 to D3 CE Q0 to Q3 VSS TC MR UP/DN CP VDD Pin description Pin 1 4, 12, 13, 3 5 6, 11, 14, 2 8 7 9 10 15 16 Description parallel load input (active HIGH) parallel input count enable input (active LOW) parallel output ground supply voltage terminal count output (active LOW) master reset input up/down count control input clock pulse input (LOW to HIGH, edge triggered) supply voltage
HEF4516B_6
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 06 -- 11 December 2009
4 of 16
NXP Semiconductors
HEF4516B
Binary up/down counter
7. Functional description
Table 3. MR L L L L H
[1]
Function table[1] PL H L L L X UP/DN X X L H X CE X H L L X CP X X X MODE parallel load no change count down count up reset
H = HIGH voltage level; L = LOW voltage level; X = don't care; = positive-going transition.
CP CE UP/DN MR PL D0 D1 D2 D3 Q0 Q1 Q2 Q3 TC count VDD VSS
5
6
7
8
9
10
11
12
13
14
15
9
8
7
6
5
4
3
2
1
0
0
15 0
001aae693
Fig 4.
Timing diagram
HEF4516B_6
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 06 -- 11 December 2009
5 of 16
NXP Semiconductors
HEF4516B
Binary up/down counter
0
1
2
3
4
15
5
14
6
13
7
12
11 count up count down
10
9
8
001aae692
Logic equation for terminal count:
TC = CE * { ( UP DN ) * Q0 * Q1 * Q2 * Q3 + ( UP DN ) * Q0 * Q1 * Q2 * Q3 } .
Fig 5. State diagram
8. Limiting values
Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VDD IIK VI IOK II/O IDD Tstg Tamb Ptot P
[1] [2]
Parameter supply voltage input clamping current input voltage output clamping current input/output current supply current storage temperature ambient temperature total power dissipation power dissipation
Conditions VI < -0.5 V or VI > VDD + 0.5 V VO < -0.5 V or VO > VDD + 0.5 V
Min -0.5 -0.5 -65 -40
Max +18 10 VDD + 0.5 10 10 50 +150 +85 750 500 100
Unit V mA V mA mA mA C C mW mW mW
DIP16 package SO16 package per output
[1] [2]
-
For DIP16 package: Ptot derates linearly with 12 mW/K above 70 C. For SO16 package: Ptot derates linearly with 8 mW/K above 70 C.
9. Recommended operating conditions
Table 5. Symbol VDD VI Tamb Recommended operating conditions Parameter supply voltage input voltage ambient temperature in free air Conditions Min 3 0 -40 Typ Max 15 VDD +85 Unit V V C
HEF4516B_6
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 06 -- 11 December 2009
6 of 16
NXP Semiconductors
HEF4516B
Binary up/down counter
Table 5. Symbol t/V
Recommended operating conditions ...continued Parameter input transition rise and fall rate Conditions VDD = 5 V VDD = 10 V VDD = 15 V Min Typ Max 3.75 0.5 0.08 Unit s/V s/V s/V
10. Static characteristics
Table 6. Static characteristics VSS = 0 V; VI = VSS or VDD unless otherwise specified. Symbol Parameter VIH HIGH-level input voltage Conditions |IO| < 1 A VDD 5V 10 V 15 V VIL LOW-level input voltage |IO| < 1 A 5V 10 V 15 V VOH HIGH-level output voltage |IO| < 1 A; VI = VSS or VDD |IO| < 1 A; VI = VSS or VDD 5V 10 V 15 V VOL LOW-level output voltage 5V 10 V 15 V IOH HIGH-level output current VO = 2.5 V VO = 4.6 V VO = 9.5 V VO = 13.5 V IOL LOW-level output current VO = 0.4 V VO = 0.5 V VO = 1.5 V II IDD input leakage current supply current VDD = 15 V IO = 0 A; VI = VSS or VDD 5V 5V 10 V 15 V 5V 10 V 15 V 15 V 5V 10 V 15 V CI input capacitance Tamb = -40 C Min 3.5 7.0 11.0 4.95 9.95 14.95 -1.7 -0.52 -1.3 -3.6 0.52 1.3 3.6 Max 1.5 3.0 4.0 0.05 0.05 0.05 0.3 20 40 80 Tamb = 25 C Min 3.5 7.0 11.0 4.95 9.95 14.95 -1.4 -0.44 -1.1 -3.0 0.44 1.1 3.0 Max 1.5 3.0 4.0 0.05 0.05 0.05 0.3 20 40 80 7.5 Tamb = 85 C Min 3.5 7.0 11.0 4.95 9.95 14.95 -1.1 -0.36 -0.9 -2.4 0.36 0.9 2.4 Max 1.5 3.0 4.0 0.05 0.05 0.05 1.0 150 300 600 V V V V V V V V V V V V mA mA mA mA mA mA mA A A A A pF Unit
HEF4516B_6
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 06 -- 11 December 2009
7 of 16
NXP Semiconductors
HEF4516B
Binary up/down counter
11. Dynamic characteristics
Table 7. Dynamic characteristics VSS = 0 V; Tamb = 25 C; for test circuit see Figure 8; unless otherwise specified. Symbol tPHL Parameter HIGH to LOW propagation delay Conditions CP to Qn VDD 5V 10 V 15 V CP to TC 5V 10 V 15 V PL to Qn 5V 10 V 15 V PL to TC 5V 10 V 15 V CE to TC 5V 10 V 15 V MR to Qn, TC 5V 10 V 15 V tPLH LOW to HIGH propagation delay CP to Qn 5V 10 V 15 V CP to TC 5V 10 V 15 V PL to Qn 5V 10 V 15 V PL to TC 5V 10 V 15 V CE to TC 5V 10 V 15 V MR to TC 5V 10 V 15 V
[1] [1]
Extrapolation formula 118 ns + (0.55 ns/pF)CL 49 ns + (0.23 ns/pF)CL 37 ns + (0.16 ns/pF)CL 233 ns + (0.55 ns/pF)CL 94 ns + (0.23 ns/pF)CL 67 ns + (0.16 ns/pF)CL 98 ns + (0.55 ns/pF)CL 44 ns + (0.23 ns/pF)CL 32 ns + (0.16 ns/pF)CL 223 ns + (0.55 ns/pF)CL 99 ns + (0.23 ns/pF)CL 72 ns + (0.16 ns/pF)CL 138 ns + (0.55 ns/pF)CL 54 ns + (0.23 ns/pF)CL 42 ns + (0.16 ns/pF)CL 178 ns + (0.55 ns/pF)CL 54 ns + (0.23 ns/pF)CL 37 ns + (0.16 ns/pF)CL 128 ns + (0.55 ns/pF)CL 54 ns + (0.23 ns/pF)CL 37 ns + (0.16 ns/pF)CL 153 ns + (0.55 ns/pF)CL 64 ns + (0.23 ns/pF)CL 47 ns + (0.16 ns/pF)CL 143 ns + (0.55 ns/pF)CL 59 ns + (0.23 ns/pF)CL 42 ns + (0.16 ns/pF)CL 223 ns + (0.55 ns/pF)CL 99 ns + (0.23 ns/pF)CL 72 ns + (0.16 ns/pF)CL 118 ns + (0.55 ns/pF)CL 49 ns + (0.23 ns/pF)CL 37 ns + (0.16 ns/pF)CL 198 ns + (0.55 ns/pF)CL 64 ns + (0.23 ns/pF)CL 42 ns + (0.16 ns/pF)CL
Min -
Typ 145 60 45 260 105 75 125 55 40 250 110 80 165 65 50 205 65 45 155 65 45 180 75 55 170 70 50 250 110 80 145 60 45 225 75 50
Max 290 120 90 525 210 150 255 110 85 500 220 160 330 135 100 405 130 85 310 130 90 360 150 115 340 140 105 500 220 160 290 125 95 450 150 100
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
HEF4516B_6
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 06 -- 11 December 2009
8 of 16
NXP Semiconductors
HEF4516B
Binary up/down counter
Table 7. Dynamic characteristics ...continued VSS = 0 V; Tamb = 25 C; for test circuit see Figure 8; unless otherwise specified. Symbol tt Parameter transition time Conditions VDD 5V 10 V 15 V fmax maximum frequency see Figure 6 5V 10 V 15 V tW pulse width CP input LOW; minimum width; see Figure 6 PL input HIGH; minimum width; see Figure 7 MR input HIGH; minimum width; see Figure 7 trec recovery time MR input; see Figure 7 5V 10 V 15 V 5V 10 V 15 V 5V 10 V 15 V 5V 10 V 15 V PL input; see Figure 7 5V 10 V 15 V tsu set-up time Dn to PL; see Figure 7 5V 10 V 15 V UP/DN to CP; see Figure 6 5V 10 V 15 V CE to CP; see Figure 6 5V 10 V 15 V th hold time Dn to PL; see Figure 7 5V 10 V 15 V UP/DN to CP; see Figure 6 5V 10 V 15 V CE to CP; see Figure 6 5V 10 V 15 V
[1]
[1]
Extrapolation formula 10 ns + (1.00 ns/pF)CL 9 ns + (0.42 ns/pF)CL 6 ns + (0.28 ns/pF)CL
Min 3 7 9 95 35 25 105 45 35 120 50 40 130 45 30 150 50 30 100 50 40 250 100 75 120 40 25 +10 +5 0 +35 +15 +15 +20 +5 +5
Typ 60 30 20 6 14 18 45 20 15 55 25 15 60 25 20 65 20 15 75 25 15 50 25 20 125 50 35 60 20 10 -40 -20 -20 -90 -35 -25 -40 -15 -10
Max 120 60 40 -
Unit ns ns ns MHz MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (CL in pF).
(c) NXP B.V. 2009. All rights reserved.
HEF4516B_6
Product data sheet
Rev. 06 -- 11 December 2009
9 of 16
NXP Semiconductors
HEF4516B
Binary up/down counter
Table 8. Dynamic power dissipation PD PD can be calculated from the formulas shown. VSS = 0 V; CL = 50 pF; tr = tf 20 ns; Tamb = 25 C. Symbol PD Parameter dynamic power dissipation VDD 5V 10 V 15 V Typical formula for PD (W) PD = 1000 x fi + (fo x CL) x VDD2 PD = 4500 x fi + (fo x CL) x VDD2 PD = 11200 x fi + (fo x CL) x VDD2 Where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VDD = supply voltage in V; (fo x CL) = sum of the outputs.
12. Waveforms
tW VM
VI CP input VSS VI CE input VSS VI UP/DN input VSS VM tsu VM
th
tsu
th
tsu
th
001aae672
Measurement points are given in Table 9.
Fig 6.
Waveforms showing minimum pulse width for CP, set-up and hold times for CE to CP and UP/DN to CP
VI CP input VSS VI PL input VSS VI Dn input VSS VI MR input VSS VM trec VM VM tW trec VM
tsu
th
tW
001aae673
Measurement points are given in Table 9.
Fig 7.
Waveforms showing PL and MR minimum pulse widths and recovery times, and Dn to PL set-up and hold times
HEF4516B_6
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 06 -- 11 December 2009
10 of 16
NXP Semiconductors
HEF4516B
Binary up/down counter
VI negative pulse 0V
tW 90 % VM 10 % tf tr tr tf 90 % VM 10 % tW
001aaj781
VM
VI positive pulse 0V
VM
a. Input waveforms
VDD VI G
RT
VO DUT
CL
001aag182
b. Test circuit
Test data is given in Table 9. Definitions for test circuit: DUT = Device Under Test CL = Load capacitance including jig and probe capacitance; RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
Fig 8. Table 9.
Test circuit for measuring switching times Measurement points and test data Input VI VM 0.5VI tr, tf 20 ns VDD Load CL 50 pF
Supply voltage 5 V to 15 V
HEF4516B_6
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 06 -- 11 December 2009
11 of 16
NXP Semiconductors
HEF4516B
Binary up/down counter
13. Package outline
DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4
D seating plane
ME
A2
A
L
A1
c Z e b1 b 16 9 b2 MH wM (e 1)
pin 1 index E
1
8
0
5 scale
10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 4.2 0.17 A1 min. 0.51 0.02 A2 max. 3.2 0.13 b 1.73 1.30 0.068 0.051 b1 0.53 0.38 0.021 0.015 b2 1.25 0.85 0.049 0.033 c 0.36 0.23 0.014 0.009 D (1) 19.50 18.55 0.77 0.73 E (1) 6.48 6.20 0.26 0.24 e 2.54 0.1 e1 7.62 0.3 L 3.60 3.05 0.14 0.12 ME 8.25 7.80 0.32 0.31 MH 10.0 8.3 0.39 0.33 w 0.254 0.01 Z (1) max. 0.76 0.03
Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION SOT38-4 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION
ISSUE DATE 95-01-14 03-02-13
Fig 9.
HEF4516B_6
Package outline SOT38-4 (DIP16)
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 06 -- 11 December 2009
12 of 16
NXP Semiconductors
HEF4516B
Binary up/down counter
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
D
E
A X
c y HE vMA
Z
16 9
Q A2 pin 1 index Lp
1 8
A1
(A 3)
A
L wM detail X
e
bp
0
2.5 scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 1.75 A1 0.25 0.10 A2 1.45 1.25 A3 0.25 0.01 bp 0.49 0.36 c 0.25 0.19 D (1) 10.0 9.8 E (1) 4.0 3.8 0.16 0.15 e 1.27 0.05 HE 6.2 5.8 L 1.05 Lp 1.0 0.4 0.039 0.016 Q 0.7 0.6 0.028 0.020 v 0.25 0.01 w 0.25 0.01 y 0.1 Z (1) 0.7 0.3
0.010 0.057 0.069 0.004 0.049
0.019 0.0100 0.39 0.014 0.0075 0.38
0.244 0.041 0.228
0.028 0.004 0.012
8 o 0
o
Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. OUTLINE VERSION SOT109-1 REFERENCES IEC 076E07 JEDEC MS-012 JEITA EUROPEAN PROJECTION
ISSUE DATE 99-12-27 03-02-19
Fig 10. Package outline SOT109-1 (SO16)
HEF4516B_6 (c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 06 -- 11 December 2009
13 of 16
NXP Semiconductors
HEF4516B
Binary up/down counter
14. Revision history
Table 10. Revision history Release date 20091211 Data sheet status Product data sheet Product data sheet Product data sheet Product specification Product specification Change notice Supersedes HEF4516B_5 HEF4516B_4 HEF4516B_CNV_3 HEF4516B_CNV_2 Document ID HEF4516B_6 Modifications: HEF4516B_5 HEF4516B_4 HEF4516B_CNV_3 HEF4516B_CNV_2
*
Section 9 "Recommended operating conditions" t/V values updated.
20090812 20090312 19950101 19950101
HEF4516B_6
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 06 -- 11 December 2009
14 of 16
NXP Semiconductors
HEF4516B
Binary up/down counter
15. Legal information
15.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control -- This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities.
15.3 Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
HEF4516B_6
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 06 -- 11 December 2009
15 of 16
NXP Semiconductors
HEF4516B
Binary up/down counter
17. Contents
1 2 3 4 5 6 6.1 6.2 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6 Recommended operating conditions. . . . . . . . 6 Static characteristics. . . . . . . . . . . . . . . . . . . . . 7 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 14 Legal information. . . . . . . . . . . . . . . . . . . . . . . 15 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 15 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Contact information. . . . . . . . . . . . . . . . . . . . . 15 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2009.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 11 December 2009 Document identifier: HEF4516B_6

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